1. Field of the Invention
The present invention relates to a ferroelectric memory, and particularly to a ferroelectric memory having a circuit structure for selecting a defective memory cell, and a method of efficiently selecting a defective memory cell lying within the ferroelectric memory with low power consumption.
This application is a counterpart of Japanese patent application, Serial Number 299875/2001, filed Sep. 28, 2001, the subject matter of which is incorporated herein by reference.
2. Description of the Related Art
A FeRAM (Ferroelectric Random Access Memory) has been known as a conventional ferroelectric memory. For instance, a 2-transistor 2-capacitor/one-bit type is known as the FeRAM. The 2-transistor 2-capacitor/one-bit type FeRAM is a FeRAM which stores one binary information by means of two memory cells, i.e., two transistors and two capacitors.
As a reference that has disclosed the FeRAM, there is known, for example, xe2x80x9cLow Power Consumption and High-Speed LSI Technology issued by Realize Co., Ltd, p.234-p.236xe2x80x9d;
A memory cell array of a general FeRAM is provided with memory cell groups arranged in matrix form. FIG. 12 shows a structure of such a memory cell array, corresponding to one sequence thereof. As shown in FIG. 12, a first memory cell M0 and a second memory cell M1 of a ferroelectric memory 2200 are respectively equipped with a first selection transistor T0, a second selection transistor T1, a first ferroelectric capacitor C0 and a second ferroelectric capacitor C1. The first ferroelectric capacitor C0 and the second ferroelectric capacitor C1 respectively store binary data therein as polarization directions. In a 2-transistor 2-capacitor/1-bit type ferroelectric memory, binary or digitized data different in value are respectively stored in ferroelectric capacitors (e.g., the first ferroelectric capacitor C0 and the second ferroelectric capacitor C1) of one memory cell pair (e.g., a pair of the first memory cell M0 and the second memory cell M1).
FIG. 13 is a timing chart for describing a data read operation of the ferroelectric memory 2200. In FIG. 13, xe2x80x98Lxe2x80x99 indicates a ground voltage, and xe2x80x98Hxe2x80x99 indicates a source voltage Vcc. Further, xe2x80x98Vhxe2x80x99 indicates a voltage which is higher than the source voltage Vcc and is increased by about a threshold voltage Vt of each of the first and second selection transistors T0 and T1.
At a time t1, the voltage applied to a precharge control line PCHG is first rendered L to turn off a first precharge transistor PCT0 and a second precharge transistor PCT1. Thus a first bit line BL0 and a second bit line BL1 are respectively brought to a floating state.
Next, the voltages applied to a first word line WL0 and a second word line WL1 are respectively set to the Vh to turn on the first selection transistor T0 and the second selection transistor T1.
When the voltage applied to a first plate line PL0 is brought to the H at a time t3, the voltage of the plate line PL0 is applied to the first bit line BL0 and the second bit line BL1 through the first ferroelectric capacitor C0, the second ferroelectric capacitor C1, the first selection transistor T0 and the second selection transistor T1, so that read voltages are developed in the first bit line BL0 and the second bit line BL1. Since the first ferroelectric capacitor C0 and the second ferroelectric capacitor C1 are different in capacitance according to the direction of polarization, the read voltages developed in the first bit line BL0 and the second bit line BL1 are also different in value from each other according to the polarization direction.
When the voltage applied to an activation signal line SAE is brought to the H at a time t4, a sense amplifier SA is activated. Thus the voltages of the first bit line BL0 and the second bit line BL1 are amplified.
The voltage of the first plate line PL0 is returned to the L at a time t5. Simultaneously, the voltage applied to a select line SEL is brought to the H. Consequently, a first bit line selection transistor SET0 and a second bit line selection transistor SET1 are turned on to output the read voltages of the first bit line BL0 and the second bit line BL1 onto a data bus 2210.
The voltage applied to the precharge control line PCHG is brought to the H at a time t6, and the voltages applied to the activation signal line SAE and the select line SEL are respectively brought to the L. Thus the first precharge transistor PCT0 and the second precharge transistor PCT1 are turned on, so that the first bit line BL0 and the second bit line BL1 are grounded and the sense amplifier SA does not output read data.
Finally, the voltages applied to the first word line WL0 and the second word line WL1 are brought to the L at a time t7 to turn off the first selection transistor T0 and the second selection transistor T1.
FIG. 14 is a conceptual diagram for describing transition of state a ferroelectric capacitor. The horizontal axis indicates a voltage V [volt], and the vertical axis indicates polarization Pr [xcexcC/cm2]. As shown in FIG. 14, the relationship between the voltage V and the polarization Pr plots or represents a hysteresis curve H. The inclination of the hysteresis curve H is equivalent to the capacitance [q/V] of the ferroelectric capacitor.
In FIG. 14, the coordinates of a point A where the hysteresis curve H and a Pr axis (region of Pr greater than 0) intersect, is defined as (0, p0). A straight line S1 is plotted which intersects, at an angle xcex8, a straight line formed by connecting the point A (0, p0) and a point B (Vcc, p0). The coordinates of a point C where the straight line S1 and an upward curve of the hysteresis curve H intersect, is defined as (v1, p1). The angle xcex8 is determined according to the capacitance of each bit line. The V coordinate v1 of the point C coincides with a terminal-to-terminal voltage of the ferroelectric capacitor, and the difference Vcc-v1 between the V coordinates of the points B and C coincides with a bit line voltage. Thus when Pr greater than 0 (when a stored value is given as xe2x80x980xe2x80x99), a voltage V0 outputted onto the corresponding bit line is represented as Vcc-V1.
In FIG. 14, the coordinates of a point D where the hysteresis curve H and the Pr axis (region of Pr less than 0) intersect, is defined as (0, p2). A straight line S2 is plotted which intersects, at the angle xcex8, a straight line formed by connecting the point D (0, p2) and a point E (Vcc, p2). The coordinate of a point F where the straight line S2 and an upward curve of the hysteresis curve H intersect, is defined as (v2, p3). Even in this case, the V coordinate v2 of the point F coincides with a terminal-to-terminal voltage of the ferroelectric capacitor, and the difference Vcc-v2 between the V coordinates of the points E and F coincides with a bit line voltage. Thus when Pr less than 0 (when a stored value is given as xe2x80x981xe2x80x99), a voltage V1 outputted onto the corresponding bit line is represented as Vcc-v2.
As is understood from FIG. 14, V0 less than V1, and the difference therebetween V1xe2x88x92V0 results in a read margin xcex94V, V0, V1 and xcex94V greatly depend on the angle xcex8, i.e., bit line capacitance Cbl.
FIG. 15 is one example of a graph showing the relationship between a ratio Cbl/Cs between the capacitance Cbl of each bit line and capacitance Cs of the ferroelectric capacitor, and the read margin xcex94V. As is understood from FIG. 15, the read margin xcex94V can be maximized by adjusting the ratio Cbl/Cs. Increasing the read margin xcex94V makes it possible to improve the reliability of read data and enhance the yield of a FeRAM.
The capacitances Cbl of the first bit line B10 and the second bit line BL1 are made up of junction capacitances of the first selection transistor T0, the second selection transistor T1, the first precharge transistor PCT0 and the second precharge transistor PCT1 connected to the first bit line BL0 and the second bit line BL1, parasitic capacitances of the first bit line BL0 and the second bit line BL1, etc. However, the majority thereof results from the junction capacitances of the first selection transistor T0 and the second selection transistor T1. In the normal FeRAM, several hundreds of selection transistors are connected to one bit line, thereby increasing the capacitances Cbl of the first bit line BL0 and the second bit line BL1.
The ferroelectric memory using the ferroelectric capacitors as described above determines the stored states of the individual memory cells according to the voltages applied to the bit lines respectively connected thereto. It is therefore necessary to ensure the voltage margins upon data reading, i.e., optimize the capacitance of each bit line. The more the read margin increases, the more misreading decreases.
Variations essentially occur in the characteristics of individual ferroelectric capacitors formed on a wafer as physical necessity of a semiconductor device. Thus a test on electric characteristics of each manufactured ferroelectric memory by means of a high voltage or the like, a durability test for activating it by an arbitrary number of times, and a thermal characteristic test for confirming its operation under the condition of a temperature higher than a normal working temperature are carried out or overloads such as a high temperature, a high voltage, etc. are applied thereto to thereby accelerate the degradation of the ferroelectric memory. In this condition, a test for allowing defects of memory cells that will be deteriorated with time in proportion as it is used, to become manifest or obvious immediately after its manufacture, thereby carrying out the selection of each memory cell is performed, followed by selection of an initial defective memory cell or a memory cell found out as defective due to its deterioration with time.
However, problems arise in that, for example, any of the tests needs to have a very long test time, a severe load must be imposed on each memory cell to be selected, and an effective degradation accelerated test cannot be carried out due to a problem about a voltage or the like depending on the specifications of a device.
The present invention has been made to solve the foregoing problems. The present invention aims to provide a ferroelectric memory provided with a circuit structure capable of selecting a defective memory cell in a very short period of time without applying an excessive load to a memory cell to be selected, and a method of efficiently selecting a defective memory cell lying within the ferroelectric memory with low power consumption.
A summary of a typical one of the inventions disclosed in the present application will be described in brief as follows:
A ferroelectric memory according to the present invention includes a plurality of memory cell pairs placed in matrix form and for respectively storing complementary digitized data therein as polarization states of ferroelectric capacitors, a plurality of bit line pairs respectively connected to the memory cell pairs lying in the same column, a plurality of word line pairs and a plurality of plate lines for respectively voltage-controlling the memory cell pairs in column units to thereby output voltages corresponding to the complementary digitized data to their corresponding bit line pairs, sense amplifiers for respectively amplifying voltages outputted to the bit line pairs, and switch transistors respectively provided for bit lines of the bit line pairs to electrically connect a predetermined number of memory cells to the respective bit line of the bit line pairs and electrically disconnect them therefrom upon selection of defective memory cells.
According to the present invention, the capacitance of each bit line can be increased upon reading data into the bit line. Since a read margin for each defective memory cell becomes extremely small apparently with the increase in the capacitance of the bit line upon the data reading, a conventionally hard-to-detect defective memory cell that will be estimated to degrade with time according to its use, can be detected and selected. Since the ferroelectric memory has a simple structure wherein the switch transistors are simply added to a circuit, the above-described effect can be obtained under a reduction in the area of the memory.